Field of the Invention
The present invention relates to a printed circuit board including a printed wiring board having a signal line being a transmission path for a signal to a first semiconductor circuit and a second semiconductor circuit.
Description of the Related Art
In recent years, with enhancement of functionality and performances of electronic equipment, the speed of data transfer between a first semiconductor circuit having an output terminal and a second semiconductor circuit having an input terminal, both of which are mounted on a printed wiring board, has been increased. Such an increased speed of data transfer may result in increased variations in propagation times of electric signals due to various kinds of noise. Such a variation in propagation time is called a jitter.
In a clock synchronization type interface, such as a Double-Data-Rate 3 Synchronous Dynamic Random Access Memory, an increased jitter may reduce the operation timing margin and thus increase the misoperation risk.
Jitters may include a jitter caused by power supply noise and a jitter caused by signal noise. The jitter caused by power supply noise will be described. First, When logic levels of signals output from output terminals of a plurality of buffer circuits in a first semiconductor circuit are simultaneously changed, current occurs. When the current is fed to a power feeding path to the first semiconductor circuit, power supply noise is caused by an impedance of the power feeding path. The power supply noise changes the power supply potential of the first semiconductor circuit, and waveforms of signals are distorted, causing jitters.
In order to reduce jitters caused by power supply noise, a capacitor may be provided between a power supply line and a ground line to lower the impedance. For preventing a rapid change of the impedance, a capacitor has been disclosed (see Japanese Patent Laid-Open No. 2007-235170) which has a low parasitic inductance (ESL) and a high parasitic resistance (ESR).
On the other hand, jitters caused by signal noise may include inter-symbol interference jitters caused due to impedance mismatching in signal wire and an insufficient frequency band and crosstalk noise jitters caused due to electromagnetic coupling between wires. In order to reduce such jitters, a terminator may be used, or an interval between wires may be increased.
An increased speed of transfer may result in a shorter interval between a rise and a fall of a signal waveform. Then, power supply noise occurring at a rise and power supply noise occurring at a fall may be superimposed, which causes a large potential fluctuation and thus increases jitters. In order to reduce jitters caused by power supply noise, the capacitor disclosed in Japanese Patent Laid-Open No. 2007-235170, for example, may be used to cause the power supply noises to be quickly converged so that the fluctuations in power supply potential may be reduced. In other words, a capacitor having a resistance component having a high resistance value disclosed in Japanese Patent Laid-Open No. 2007-235170 may be mounted in vicinity of the first semiconductor circuit (such as a plane on the opposite side of the plane mounting the first semiconductor circuit) to cause the power supply noise to be quickly converged.
However, because electromagnetic coupling is provided between the signal wire and the power plane, noise may be propagated from the signal wire to the power plane, causing resonance noise from the power plane. The resonance noise may also cause jitters due to signal noise. (See Jingook Kim, et al, “Analytical Model of power/ground noise coupling to signal traces in high-speed multi-layer package or boards.” IEEE 5th Electronics Packaging Technology Conference, pp. 45-50, December 2003.) In other words, noise caused by the power plane resonance is propagated from the power plane to the signal line because of their electromagnetic coupling, and jitters may thus occur.
In order to prevent the propagation of noise to a signal line, a capacitor which apply a bypass to a power plane and a ground plane may be provided in the second semiconductor circuit having an input terminal power to inhibit plane resonance noise and thus reduce jitters due to the signal noise.
Because a power supply plane and a signal line co-exist on a printed circuit board, implementation of a combination of a measure against power supply noise and a measure against signal noise may be necessary. While the capacitor to be inserted to the first semiconductor circuit for prevention of power supply noise is a component having a high resistance value for quick convergence of power supply noise, a capacitor to be inserted to a second semiconductor circuit for prevention of signal noise is a component having a low resistance value. Thus, a combination of the two measures against noise facilitates flow of power supply noise occurring during an operation of the first semiconductor circuit to a capacitor having a resistance component with a low resistance value inserted to the second semiconductor circuit. Therefore, though the effect of signal noise reduction produced by the capacitor inserted to the second semiconductor circuit could be maintained. The effect of attenuation of power supply noise is lowered, which reduce the effect of reduction of jitters due to power supply noise.
The present invention provides a printed circuit board which may reduce jitters due to power supply noise even with a combination of a first bypass circuit and a second bypass circuit.